A) Field of the Invention
The present invention relates to a semiconductor device manufacture method, and more particularly to a semiconductor device manufacture method having a process of forming wirings by filling concave portions formed in an insulating film with conductor having Cu as its main composition.
B) Description of the Related Art
Miniaturization of wirings and increasing of wiring layers are progressing as semiconductor elements are highly integrated and chip sizes are reduced. In a logical element having a multi-layer wiring structure, a delay of a signal transmitting along a wiring is becoming a dominant factor of lowering an operation speed of the logical element. The delay of a signal transmitting along a wiring is proportional to a product of a wiring resistance and a parasitic capacitance between wirings.
Technologies of using copper (Cu) having a low resistivity as wiring material are adopted practically in order to reduce wiring resistance. Since it is difficult to pattern a copper film by using photolithography process, a damascene method is generally adopted to form copper wirings.
When a copper wiring is formed by the damascene method, the inner surface of a wiring trench and a via hole is covered with a barrier layer before the copper film is deposited, the main object of the barrier layer being to prevent diffusion of copper into an insulating film. Refractory metal such as tantalum (Ta) and tungsten (W) is used as the material of a barrier film. Refractory metal has a resistivity higher than that of copper.
As the size of a wiring becomes fine, a ratio of the barrier layer occupying the cross section of the wiring becomes large. Therefore, the barrier layer has a large factor of raising a wiring resistance. Especially, in a fine multi-layer wiring structure having a diameter and wiring width of a via hole of 0.1 μm or smaller, it is desired to make the barrier layer as thin as possible.
Chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like are considered hopeful as techniques of forming a thin barrier layer. If these film forming methods are adopted by using low dielectric constant material as the material of an interlayer insulating film, a sufficient tight adhesion cannot be obtained.
The document “Low-temperature passivation of copper by doping with Al or Mg” by W. A. Lanford et al., Thin Solid Films, 262(1995), pp. 234 to 241 discloses the technique of forming an Al oxide or Mg oxide layer on the surface of Cu by doping Al or Mg into Cu and performing heat treatment. This oxide layer functions as a protective film and diffusion preventing film for Cu.
Next, description will be made on a method of forming a thin barrier layer having a uniform thickness, disclosed in the document “Low Resistive and Highly Reliable Cu Dual-Damascene Interconnect Technology Using Self-Formed MnSixOy Barrier layer” by T. Usui et al., IITC 2005, Session 9.2. A seed layer of CuMn alloy is formed by sputtering on the surface of an interlayer insulating film formed with wiring trenches and via holes. Thereafter, copper is electroplated to fill the wiring groove and via hole with the copper. Heat treatment is performed to react Si and O as the constituent elements in the interlayer insulating film with Mn as the constituent element in the seed layer. A barrier layer is therefore formed at the interface between a Cu wiring and the interlayer insulating film, the barrier layer being made of MnSixOy compound which is very thin about 2 to 3 nm in thickness and has a uniform thickness. This barrier layer prevents diffusion of Cu.
The seed layer covering the bottom of the via hole does not contact the interlayer insulating film and contacts a lower level wiring. Therefore, the barrier layer is not formed at the interface between the copper wiring in the via hole and the lower level wiring, so that the upper and lower level wirings can be connected without the barrier layer between the upper and lower level wirings. Further, since the barrier layer made of MnSiO compound can be made thinner than a barrier layer made of refractory metal, it is possible to suppress an increase of wiring resistance.
With reference to FIG. 5A and 5B, description will be made on a conventional method for forming a Cu wiring. As shown in FIG. 5A, a concave portion 100A corresponding to a wiring trench, a via hole and the like is formed in an insulating film 100 made of SiOC, porous silica or the like. The inner surface of the concave portion 100A and the upper surface of the insulating film 100 are covered with an auxiliary film 101 made of CuMn alloy. Cu is deposited on the auxiliary film 101 to form a conductive member 102 by electroplating, filling the concave portion 100A. After the conductive member 102 is formed, heat treatment is performed in an oxidizing atmosphere.
FIG. 5B is a cross sectional view of the semiconductor substrate after the heat treatment. Mn as the constituent element of the auxiliary film 101 is segregated on the surface of the insulation film 100. The segregated Mn reacts with Si and O in the insulation film 100 to form a barrier layer 105 made of MnSiO compound. Part of Mn diffuses in the conductive member 102 and reaches the surface thereof. Mn reached the surface reacts with oxygen in the heat treatment atmosphere to form a cover film 106 made of manganese oxide. In this manner, since Mn is consumed by the barrier layer 105 and cover film 106, a Mn content in the conductive member 102 can be reduced. Namely, it is possible to raise the purity of Cu of the conductive member 102 and prevent a resistivity from being increased by impurities.
FIG. 6 is a graph showing the relation between an in-chamber pressure during heat treatment and a resistivity of the conductive member 102 after heat treatment. The abscissa represents a pressure in the unit of “mPa”, and the left end indicates no-annealing. The ordinate represents a resistivity in the unit of “μΩcm”. Circle, triangle, rhombus and square symbols shown in FIG. 6 indicate the resistivity of insulating films made of thermally oxidized silicon oxide, porous methylsilsequioxane (porous MSQ), SiNC and SiOC, respectively. Heat treatment was performed at 400° C. for 30 minutes in an oxygen atmosphere.
It can be seen that heat treatment lowers the resistivity. It was anticipated that as the pressure was raised, oxidation reaction of Mn at the surface of the conductive member 102 could progress and the resistivity could be lowered. However, even if the pressure is raised, the resistivity lowered only to about 3 μΩcm. The resistivity of pure copper is about 1.67 μΩcm.
Description will be made on why the resistivity does not lower to the value of pure copper. If the cover film 106 of manganese oxide becomes thick to some extent, the cover film 106 itself suppresses diffusion of Mn and O and oxidation reaction of Mn becomes hard to occur. Mn in the conductive member 102 will not reduce further. It can be considered that since Mn is resident in the conductive member 102, the resistivity lowers only to about 3 μΩcm.